1.9 Performance

User Instruction Latency and Repeat Rate

Table 1-2 Latencies and Repeat Rates for User Instructions

Please note the following about Table 1-2:

• For integer instructions, conditional trap evaluation takes a single cycle, like conditional branches.
• Branches and conditional moves are not conditionally issued.
• The repeat rate above for Load/Store does not include Load Link and Store Conditional.
• Prefetch instruction is not included here.
• The latency for multiplication and division depends upon the next instruction.
• An instruction using register Lo can be issued one cycle earlier than one using Hi.
• For floating-point instructions, CP1 branches are evaluated in the Graduation Unit.
• CTC1 and CFC1 are not included in this table.
• The repeat pattern for the CVT.S.(W/L) is "I I x x I I x x ..."; the repeat rate given here, 2, is the average.
• The latency for MADD instructions is 2 cycles if the result is used as the operand specified by fr of the second MADD instruction.
• Load Linked and Store Conditional instructions (LL, LLD, SC, and SCD) do not implicitly perform SYNC operations in the R10000. Any of the following events that occur between a Load Linked and a Store Conditional will cause the Store Conditional to fail: an exception; execution of an ERET, a load, a store, a SYNC, a CacheOp, a prefetch, or an external intervention/invalidation on the block containing the linked address. Instruction cache misses do not cause the Store Conditional to fail.
• Up to four branches can be evaluated at one cycle.*1